For providing overlapped displays of characters and graphics on a cathode ray tube (CRT) display or similar display unit, it is customary in the art to employ such a memory (RAM) constitution as shown in FIGS. 4A and 4B for a screen configuration depicted in FIG. 3.
In FIG. 3 the screen is 80 characters wide by 25 rows long. Generally characters are each composed of n lines for a single piece of display data (a character), and accordingly, lines of characters are each displayed in sequence; for example, when n=16, a line 0 of characters 0 to 79 is displayed, then a line 1 of characters 0 to 79 is displayed, followed by the subsequent lines of characters.
Conventionally, display data are arranged on the RAM as shown in FIGS. 4A and 4B so as to produce such a display as mentioned above.
FIG. 4A shows a memory constitution for characters, in which characters 0 to 79 of a first row, composed of 16 lines, are written in addresses 00000H to 0007FH and characters 80 to 159 of a second row are written in addresses 00080H to 000FFH. Similarly, characters of each of the subsequent rows are assigned addresses by steps of 80H; thus, characters of 25 rows are arranged on the memory. This is because the address structure is simplified by an arrangement in which the transition from one row composed of 80 characters, each 1 byte (=8 dots) wide, to the next row is made by shifting the high-order bit of the address of the preceding row by a predetermined number to the leading address of each line of the next row. To perform this, and unused area (a remainder) is provided at the end of each row.
FIG. 4B shows the arrangement of graphic data on the memory, in which graphic data corresponding to the first row of characters are arranged for each line; namely, data of a first line .circle.1 are written in addresses 10000H to 1007FH and then data of a second line .circle.2 are written in addresses 10080H to 100FFH. Similarly the subsequent lines are each assigned 80H addresses; thus, graphic data of 16 lines corresponding to the first row of character data are arranged on the memory. Next, graphic data corresponding to the second line of character data are similarly arranged for each line on the memory. In this way, graphic data corresponding to character data of 25 rows are arranged on the memory. In this instance, an unused area is provided at the end of each line as is the case with the character data. In the manner described just above, graphic data, including that corresponding to the last character of the 25th row, are arranged on the memory. The data thus arranged on the memory are read out in the order of .circle.1 , .circle.2 , . . . , .circle.16 , .circle.17 , . . . , .circle.400 .
With the data arrangement on the memory shown in FIG. 4B, unused areas are provided at the ends of the rows and the lines so that the transition to the next character or line is made of shifting the high-order bit of the address of the preceding row or line by a predetermined number to the leading address of the next character or line, thereby simplifying the address structure.
The conventional method of data arrangement on the RAM depicted in FIGS. 4A and 4B have the defect that the overall utilization efficiency of the RAM is poor, because the unused area is provided for each row of character data and for each line of graphic data.